//--------------------------------------------------------------------
//		Timescale
//		Means that if you do #1 in the initial block of your
//		testbench, time is advanced by 1ns instead of 1ps
//--------------------------------------------------------------------
`timescale 1ns / 1ps
//--------------------------------------------------------------------

//--------------------------------------------------------------------
//		The Lab4FSM Testbench. You will need to write this entire
//		testbench on your own. Use Lab4BasicTestbench as an example.
//--------------------------------------------------------------------
module Lab4FSMTestbench();

	//----------------------------------------------------------------
	//		Parameters
	//----------------------------------------------------------------
	parameter HalfCycle		= 5;			//Half of the Clock Period is 5 ns
	//----------------------------------------------------------------

	//----------------------------------------------------------------
	//		Constants
	//----------------------------------------------------------------
	localparam Cycle		= 2*HalfCycle;	//The length of the entire Clock Period
	//----------------------------------------------------------------

	/* You will need to write everything else on your own */	

	//----------------------------------------------------------------
	//		Test Stimulus
	//----------------------------------------------------------------
	integer i, j;
	
	reg [8:0] TestValues [7:0];
	
	reg Clock;
	reg Reset;
	reg In, expected;
	reg [2:0] expectedState;
	
	wire Out;
	wire [2:0] State;
	
	initial Clock	= 0;				//Clock is at 0 at time 0 of the simulation
	always #(HalfCycle) Clock = ~Clock;	//Every half of a Clock period, flip the Clock
	Lab4FSM DUT(.Clock(Clock), .Reset(Reset), .In(In), .Out(Out), .State(State));
	
	
	initial begin
		#(10*Cycle);	//PLEASE LEAVE THIS HERE! This is required because the
						//simulation model of an FDRSE flip flop will not respond
						//to any inputs for the first 100ns of simulation
		$readmemb("TestValues.txt", TestValues);
		
		for (i = 0; i < 7; i = i+1) begin
			#(Cycle) Reset = 1;
			#(Cycle) Reset = 0;
			for (j = 0; j < 6; j = j +1) begin
				$display("old state %d new input %b", State, In);
				#(Cycle) In = TestValues[i][j];
				$display("current state %d after input", State);
			end
			expected = TestValues[i][8:6];
			if(expected != State) $display("mismatch at index %b actual is %b", TestValues[i], State);
		end
	/* You will need to complete this section on your own */
	
	end
	//----------------------------------------------------------------


endmodule
